DATA_CRC_ERR=Val_0x0, ADMA_ERR=Val_0x0, CMD_IDX_ERR=Val_0x0, BOOT_ACK_ERR=Val_0x0, CMD_END_BIT_ERR=Val_0x0, CUR_LMT_ERR=Val_0x0, CMD_CRC_ERR=Val_0x0, RESP_ERR=Val_0x0, DATA_END_BIT_ERR=Val_0x0, DATA_TOUT_ERR=Val_0x0, AUTO_CMD_ERR=Val_0x0, CMD_TOUT_ERR=Val_0x0
Error Interrupt Status Register
| CMD_TOUT_ERR | Command Timeout Error. in SD or eMMC modes, this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict, along with the SDMMC_ERROR_INT_STAT_R[CMD_CRC_ERR] bit, this bit is set to 0x1, without waiting for 64 SD or eMMC card clock cycles. 0 (Val_0x0): No error 1 (Val_0x1): Time out. Write 0x1 to clear. |
| CMD_CRC_ERR | Command CRC Error. Command CRC Error is generated in SD or eMMC modes for following two cases. If a response is returned and the Command Timeout Error (SDMMC_ERROR_INT_STAT_R[CMD_TOUT_ERR]) is set to 0x0 (indicating no timeout), this bit is set to 0x1 when detecting a CRC error in the command response. The Host Controller detects a CMD line conflict by monitoring the CMD line when a command is issued. If the Host Controller drives the CMD line to 0x1 level, but detects 0x0 level on the CMD line at the next SD clock edge, then the Host Controller aborts the command (stop driving CMD line) and set this bit to 0x1. The SDMMC_ERROR_INT_STAT_R[CMD_TOUT_ERR] bit is also set to 0x1 to distinguish a CMD line conflict. 0 (Val_0x0): No error 1 (Val_0x1): CRC error generated. Write 0x1 to clear. |
| CMD_END_BIT_ERR | Command End Bit Error. This bit is set when detecting that the end bit of a command response is 0x0 in SD or eMMC modes. 0 (Val_0x0): No error 1 (Val_0x1): End bit error generated. Write 0x1 to clear. |
| CMD_IDX_ERR | Command Index Error. This bit is set if a Command Index error occurs in the command response in SD or eMMC modes. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| DATA_TOUT_ERR | Data Timeout Error. This bit is set in SD or eMMC modes when detecting one of the following timeout conditions:
0 (Val_0x0): No error 1 (Val_0x1): Time out. Write 0x1 to clear. |
| DATA_CRC_ERR | Data CRC Error. This error occurs in SD or eMMC modes when detecting CRC error when transferring read data which uses the DAT line, when detecting the Write CRC status having a value of other than 0x0 or when write CRC status timeout. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| DATA_END_BIT_ERR | Data End Bit Error. This error occurs in SD or eMMC modes either when detecting 0x0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| CUR_LMT_ERR | Current Limit Error. By setting the SD Bus Power bit in the SDMMC_PWR_CTRL_R register, the Host Controller is requested to supply power for the SD Bus. If the Host Controller supports the Current Limit function, it can be protected from an illegal card by stopping power supply to the card in which case this bit indicates a failure status. A reading of 0x1 for this bit means that the Host Controller is not supplying power to the SD card due to some failure. A reading of 0x0 for this bit means that the Host Controller is supplying power and no error has occurred. The Host Controller may require some sampling time to detect the current limit. If the SDMMC Host Controller does not support this function, this bit is always set to 0x0. 0 (Val_0x0): No error 1 (Val_0x1): Power Fail. Write 0x1 to clear. |
| AUTO_CMD_ERR | Auto CMD Error. This error status is used by Auto CMD12 and Auto CMD23 in SD or eMMC modes. This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0x0 to 0x1. D07 is effective in case of Auto CMD12. The Auto CMD Error Status register is valid while this bit is set to 0x1 and may be cleared by clearing of this bit. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| ADMA_ERR | ADMA Error. This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to Error response received from System bus (Master interface)-ADMA3, ADMA2 Descriptors invalid 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| RESP_ERR | Response Error. Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by the Host Driver during DMA execution. If the SDMMC_XFER_MODE_R[RESP_ERR_CHK_ENABLE] bit is set to 0x1, the Host Controller checks R1 or R5 response. If an error is detected in a response, this bit is set to 0x1. This is applicable in SD or eMMC modes. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| BOOT_ACK_ERR | Boot Acknowledgement Error. This bit is set when there is a timeout for boot acknowledgement or when detecting boot ACK status having a value other than 0x0. This is applicable only when boot acknowledgement is expected in eMMC mode. 0 (Val_0x0): No error 1 (Val_0x1): Error. Write 0x1 to clear. |
| VENDOR_ERR1 | Reserved. It always returns 0x0. |
| VENDOR_ERR2 | Reserved. It always returns 0x0. |
| VENDOR_ERR3 | Reserved. It always returns 0x0. |